1. Technical Field
Various embodiments of the present invention relate to a nonvolatile memory apparatus and a method for driving the same and, more particularly, to a flash memory apparatus and a related driving method, which may reduce current consumption of unselected bit lines.
2. Related Art
Flash memories are nonvolatile memory apparatuses that are widely used in portable electronic devices (e.g., notebooks, PDAs (personal digital assistants), and mobile phones), computer BIOSs (basic input/output systems), printers, and other various electronic parts such as USB (universal serial bus) drivers.
Such flash memories can be divided into a NAND-type and a NOR-type. Currently, NAND type flash memories are mainly used in consideration of an integration density and other reasons.
A NAND-type flash memory includes a plurality of memory cell blocks. Each of the memory cell blocks includes a drain select transistor, a source select transistor, and a memory cell string connected therebetween. The cell string refers to a device having, for example, 16 or 32 MOS transistors connected in series. These memory cell blocks are grouped to form a memory cell array.
FIG. 1 is a schematic circuit diagram illustrating a conventional flash memory. The flash memory of FIG. 1 includes a page buffer 15 to which a plurality of bit lines Even BL and Odd BL are coupled.
Each of the bit lines Even BL and Odd BL has a memory cell string ST in which a plurality of memory transistors T1-Tn are coupled in series. Drain select transistors (DST) 20 are coupled between memory cell strings ST and the bit lines Even BL and Odd BL, and source select transistors (SST) 30 are coupled between the memory cell strings ST and a source line SL.
The memory transistors T1-Tn of the cell strings ST are respectively driven in response to the signals of corresponding word lines WL0-WLn, the drain select transistors 20 are driven in response to the signal of a drain select line DSL, and the source select transistors 30 are driven in response to the signal of a source select line SSL.
In a flash memory having the above-described configuration, programming and verification steps are performed each bit line at a time as a unit. When performing a programming and/or verification step on a selected bit line, a specific voltage is discharged to the unselected bit line so as to shield the unselected bit line from performing programming or verification. For example, the unselected bit line is continuously applied with a driving voltage in a programming step to shield the unselected bit line and is applied with 0V voltage in a verification step to be discharged.
Thus, in the conventional flash memory, a prescribed voltage is applied to the unselected bit line to prevent it from driving when programming data to a predetermined memory cell, and 0V is applied to the unselected bit line when performing a verification step. Because a voltage swing in each of the steps is substantial, current consumption of the flash memory increases.